On-chip interconnection network

Copublished by the IEEE CS and the IEEE CASS September–October 2005 IT IS OUR PLEASURE TO INTRODUCE this special issue on networks on chips (NoCs). Large, complex multiprocessor-based SoC platforms are already well into existence, and, according to common expectations and technology roadmaps, the emergence of billion-transistor chips is just around the corner. The complexity of such systems calls for a serious revisiting of several onchip communication issues. In this special issue, we focus on an emerging paradigm that effectively addresses and presumably can overcome the many on-chip interconnection and communication challenges that already exist in today’s chips or will likely occur in future chips. This new paradigm is commonly known as the network-on-chip paradigm. The articles featured in this issue come from outstanding experts from around the world, from both industry and academia. Together, the articles reveal and discuss a wide range of issues specifically pertinent to NoCs. They also provide perspective based on actual practice, as well as more-speculative perspectives. To achieve a good degree of self-containment in this issue, we’ve included a more tutorial/survey type of article to lead a group of four specific and detailed articles. The NoC paradigm is one, if not the only one, fit to enable the integration of an exceedingly large number of computational, logic, and storage blocks in a single chip (otherwise known as a SoC). Notwithstanding this school of thought, the adoption and deployment of NoCs face important issues relating to design and test methodologies and automation tools. In many cases, these issues remain unresolved. On-chip interconnection network Set-top boxes, wireless base stations, high-definition TV, and mobile handsets are just a few applications that have arisen because of multiprocessor SoCs. With such chips, the constraints for performance, power consumption, reliability, error tolerance and recovery, cost, and so forth can be extremely severe. One design characteristic that lies at the core of all these critical specifications is the on-chip interconnection network. Many experts advocate regularity in such networks as opposed to continuing with the more traditional ad hoc networks that have evolved over the past decades of IC design. Hence, much research and practical interest has recently focused on regular networks implemented on chip, often influenced by the parallel-computing field. When integrated on chip in the form of micronetworks, these regular networks are referred to as NoCs. Effective on-chip implementation of networkbased interconnect paradigms requires developing and deploying a whole new set of infrastructure IPs and supporting tools and methodologies. For example, NoCs require switches and router blocks, as well as corresponding communication formats and protocols. The design complexity of conventional SoCs is already soaring, so it’s understandable that the development of SoCs based on nontraditional models might at first appear overwhelming and hence unnecessary or undesirable. However, when the specifications of these systems reach levels at which traditional methodologies and architectures are incapable of meeting the requirements, system architects and project managers obviously have no recourse except Guest Editors’ Introduction: The Network-on-Chip Paradigm in Practice and Research